0 or 3 credits
Spring 2026 Laboratory Lecture Upper Division
This course introduces students to various contemporary Hardware Description Languages (HDL) for modern digital logic systems. The course will emphasize on Verilog HDL. It covers logic-synthesis and high-level-synthesis in the context of HDL coding constructs for platform-independent and dependent technologies applicable to modern semiconductor industry testing. Students are also exposed to the subset of HDL that may be used for synthesis of custom logic for edge devices. HDL simulation and synthesis labs and projects are performed using commercial and/or academic VLSI CAD tools.
Learning Outcomes1Gain proficiency in popular HDL for modeling digital systems.
2Use CAD tools to synthesize HDL code.
3Verify/validate results through simulation and testing.
4Identify effective HDL constructs for reconfigurable programmable logic vs. custom logic.
5Apply HDL in real-world projects, including the development of complex digital systems for emerging technologies.
Prerequisites
made by Purdue students.