GPA

3.54

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Discusses different aspects of VLSI testing and formal verification of designs. Design and manufacturing defect models are introduced along with test generation and fault simulation algorithms targeting the different fault models. Both combinational and sequential logic testing are covered, and different synthesis for testability schemes such as BIST (Built-In-Self-Test), scan path design, etc., are introduced. Other new and emerging test and verification techniques also are discussed. Offered every third semester. Prerequisite: ECE 55900.

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